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    block this user An-Ping Li

    Research Fellow

    Beijing 100085, P.R.China

    Partitioning Algorithms And Parallel Implementations Of Waveform Relaxation Algorithms For Circuit Simulation

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    Since the first applications of Waveform Relaxation (WR) algorithms to the transient analysis of MOS digital circuits, several modifications to the basic method have been used to improve WR efficiency and insure convergence. In particular. convergence problems related to tight feedb.ack loops and inac- curate subcircuit solutions have been addressed and solved with the use of theoretically justified techniques such as dynamic windowing and adaptive error control. However. in order to get reasonably rapid convertfence of the the WR method. it is a[so necessary to partition a arge circuit into loosely coupled subcir- cuits. In this paper a numerically based partitioning method is presented that attempts to break a large circuit into loosely coupled subcircuits by examining estimates for the speed of convergence of the relaxation iteration for candidate partitions. This new partitioning technique has been implemented in the WR based circuit si/:nulator IELAX2.3 and r-esults from that pro- gram are presented. Finally. the implementation of the WR algorithm on parallel processors will be presented.

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    Title : Partitioning Algorithms And Parallel Implementations Of Waveform Relaxation Algorithms For Circuit Simulation
    Abstract : Since the first applications of Waveform Relaxation (WR) algorithms to the transient analysis of MOS digital circuits, several modifications to the basic method have been used to improve WR efficiency and insure convergence. In particular. convergence problems related to tight feedb.ack loops and inac- curate subcircuit solutions have been addressed and solved with the use of theoretically justified techniques such as dynamic windowing and adaptive error control. However. in order to get reasonably rapid convertfence of the the WR method. it is a[so necessary to partition a arge circuit into loosely coupled subcir- cuits. In this paper a numerically based partitioning method is presented that attempts to break a large circuit into loosely coupled subcircuits by examining estimates for the speed of convergence of the relaxation iteration for candidate partitions. This new partitioning technique has been implemented in the WR based circuit si/:nulator IELAX2.3 and r-esults from that pro- gram are presented. Finally. the implementation of the WR algorithm on parallel processors will be presented.
    Subject : unspecified
    Area : Mathematics
    Language : English
    Affiliations
    Url : http://rleweb.mit.edu/vlsi/publications/pub80.pdf
    Doi : 10.1.1.19.8591

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    An-Ping's Peer Evaluation activity

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