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    Vienna University of Technology, Institute of Computer Technology

    Late Hardware/Software Partitioning by Using SystemC Functional Models

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    In this paper a partly unified hardware/software design flow is presented. It uses System C as system level design language and postpones the partitioning decision to a lower abstraction level by using a realization independent functional model. Especially the partitioning of data flow dominant tasks between hardware and software is simplified with this approach. Additionally, by using a C-based design language for hardware and software design, system simulations at different abstraction levels are simplified. In combination with the concept of high level synthesis, this design flow reduces the effort after the partitioning and thus also significantly reduces the extra effort of a possible re partitioning between hardware and software. As proof of concept the receiver components of a VoIP engine have been implemented. The data flow dominant RTP protocol has been realized on an FPGA and the results of different hardware/software partitionings are presented.

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    Description

    Title : Late Hardware/Software Partitioning by Using SystemC Functional Models
    Author(s) : Peter Brunmayr, Jan Haase, Florian Schupfer
    Abstract : In this paper a partly unified hardware/software design flow is presented. It uses System C as system level design language and postpones the partitioning decision to a lower abstraction level by using a realization independent functional model. Especially the partitioning of data flow dominant tasks between hardware and software is simplified with this approach. Additionally, by using a C-based design language for hardware and software design, system simulations at different abstraction levels are simplified. In combination with the concept of high level synthesis, this design flow reduces the effort after the partitioning and thus also significantly reduces the extra effort of a possible re partitioning between hardware and software. As proof of concept the receiver components of a VoIP engine have been implemented. The data flow dominant RTP protocol has been realized on an FPGA and the results of different hardware/software partitionings are presented.
    Subject : unspecified
    Area : Other
    Language : English
    Year : 2009

    Affiliations Vienna University of Technology, Institute of Computer Technology
    Journal : 2009 Third Asia International Conference on Modelling Simulation
    Publisher : IEEE
    Pages : 194 - 199
    Url : http://ieeexplore.ieee.org/lpdocs/epic03/wrapper.htm?arnumber=5071982
    Isbn : 978-1-4244-4154-9
    Doi : 10.1109/AMS.2009.18

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