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    block this user Konstantinos Glaros

    Student, Ph.D. Level

    Imperial College London

    Insights and Advances on the Design of CMOS Sinh Companding Filters

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    The scope of this paper is to present certain insights and advances towards the synthesis and transistor-level implementation of high dynamic range (> 120 dB), micropower, CMOS Sinh companding filters. In particular, we present detailed technical insights on a recently proposed Sinh integrator which may serve as the basic building block for higher-order filter structures. The particular integrator exhibits a promising simulated linearity performance mainly because it does not rely on the complementarity of both N- and P-type MOS transistors to achieve its Class-AB operation. Rather, it is designed with single-type devices in its signal processing path. The integrator is evaluated through detailed simulation results obtained by performing both large-signal transient and periodic steady-state (PSS) analyses in Cadence IC Design Frameworkreg with the parameters of the commercially available AMS 0.35-mum CMOS process. SNR, SNDR, IP3 and mismatch are some of the performance figures reported in this work. A detailed head-to-head comparison with a typical pseudo-differential Class-AB Log-domain integrator, designed in the same technology and with identical specifications, is also performed in order to reveal any potential benefits of the Sinh circuit paradigm.

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    Description

    Title : Insights and Advances on the Design of CMOS Sinh Companding Filters
    Author(s) : K. N. Glaros, A. G. Katsiamis, E. M. Drakakis
    Abstract : The scope of this paper is to present certain insights and advances towards the synthesis and transistor-level implementation of high dynamic range (> 120 dB), micropower, CMOS Sinh companding filters. In particular, we present detailed technical insights on a recently proposed Sinh integrator which may serve as the basic building block for higher-order filter structures. The particular integrator exhibits a promising simulated linearity performance mainly because it does not rely on the complementarity of both N- and P-type MOS transistors to achieve its Class-AB operation. Rather, it is designed with single-type devices in its signal processing path. The integrator is evaluated through detailed simulation results obtained by performing both large-signal transient and periodic steady-state (PSS) analyses in Cadence IC Design Frameworkreg with the parameters of the commercially available AMS 0.35-mum CMOS process. SNR, SNDR, IP3 and mismatch are some of the performance figures reported in this work. A detailed head-to-head comparison with a typical pseudo-differential Class-AB Log-domain integrator, designed in the same technology and with identical specifications, is also performed in order to reveal any potential benefits of the Sinh circuit paradigm.
    Keywords : ELIN systems, companding

    Subject : unspecified
    Area : Electronic Engineering
    Language : English
    Year : 2008

    Affiliations Imperial College London
    Journal : IEEE Transactions on Circuits and Systems I: Regular Papers
    Volume : 55
    Issue : 9
    Publisher : IEEE
    Pages : 2539-2550
    Url : http://ieeexplore.ieee.org/xpl/freeabs_all.jsp?arnumber=4490289
    Doi : 10.1109/TCSI.2008.921037

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